The goal of this course is to provide a deep understanding of the fundamental principles and engineering tradeoffs involved in designing modern parallel computers (aka "multiprocessors" and "multicore"), as well as the programming techniques to effectively utilized these machines. Parallel machines are already ubiquitous from desktops to supercomputers, and the expectation is that they will become even more commonplace in the future. However, very few people exploit the potential processing power of these machines because they do not understand how to write efficient parallel programs.

Because one cannot design a good parallel program without understanding how parallel machines are built and vice-versa, this course will cover both parallel hardware and software design, as well as the impact that they have on each other.

Course topics include naming shared data, synchronizing threads, and the latency and bandwidth associated with communication. Case studies on shared-memory, message-passing, data-parallel and dataflow machines will be used to illustrate these techniques and tradeoffs. Programming assignments will be performed on one or more commercial multiprocessors, and there will be a significant course project.

This is a relatively unique course since this material is rarely offered to undergraduates. Because parallel processing has become such an important and mainstream technology, the time has come to integrate this material into the undergraduate systems curriculum.

Dr. Todd Mowry, Carnegie Mellon University, authored this course. It is serves as one of the first undergrad courses focusing on parallel architecture and programming.

• Complete Syllabus

Week	Lecture Topics	Homework	Reading	Exam
1	1.Why Parallel Architecture? 2.Evolution and Convergence 3.Fundamental Design Issues		1.1 1.2 1.3-4
2	4-5.Parallel Programming: Overview Initiate Lecture 6	Assignment #1 Issued	2.1-2 2.3-4 3.1
3	6-8.Parallel Programming: Performance 9.Parallel Programming: 9a. Case Studies 9b. Implications for Programming Models	Assignment #2 Issued	3.2 3.3-4 3.5-6
4	10-11.Workload-Driven Architecture Evaluation Initiate Lecture 12	Assignment #1 Due	4.1 4.2-3 5.1
5	12-14.Shared Memory Multiprocessors Initiate Lecture 15	Assignment #3 Issued	5.3 5.4 8.1-5
6	15-16.Directory-Based Cache Coherence 17.Memory Consistency Models Initiate Lecture 18	Assignment #2 Due	8.6-7, 8.9-11 9.1 6.1
7	18-22.Snoop-Based Multiprocessor Design		6.2-4 6.5-7	Exam 1
8	23.Synchronization Catch up week	Assignment #3 Due Term Project Proposal Due Term Project Administrative Info	5.5 7.9 8.8
9	24-25.Scalable Distributed Memory Multiprocessors 26.Interconnection Network Design		7.1-3 7.4-8 10.1-10
10	27.Latency Tolerance: Prefetching 28.Latency Tolerance: Multithreading	Term Project: Milestone #1 Due	11.1, 11.6 11.7-9
11-12		Term Project: Milestone #2 Due		Exam 2
13-14	Project Poster Session	Term Project Due

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